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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93C071
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (INT0, INT1), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fc or fs) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP93C071
CMOS 16-Bit Microcontroller
TMP93C071F 1. Outline and Feature
TMP93C071F is a high-speed advanced 16-bit microcontroller developed for application with VCR system control, software servo motor control and timer control. In addition to basics such as I/O ports, the TMP93C071F has high-speed/high-precision signal measuring circuit, PWM (Pulse-Width-Modulator) and high-precision real timing pulse generator. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions High-speed micro DMA: 4 channels (1.6 s/2 byte at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal ROM: ROMless (4) Internal RAM: 8 Kbytes (5) External memory expansion Can be expanded up to 16 Mbytes (for both programs and data) AM 8/16 pin (select the external data bus width) Can be mixed 8- and 16-bit external data buses. Dynamic data bus sizing. (6) 20-bit time-base-counter (TBC) Free running counter Accuracy: 100 ns (at 20 MHz) Overflow: 105 ms (at 20 MHz)
000707EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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(7) 8-bit timer (TC0): 1 channel CTL linear time counter (8) 16-bit timer (TC1 to 5): 5 channels C.sync count, capstan FG count, general: (3 channels) (9) Timing pulse generator (TPG): 2 channels (16-bit timing data (16-bit timing data 6-bit-output data) with 8-stages FIFO: 1 channel 4-bit-output data): 1 channel
Accuracy: 400 ns (at 20 MHz) (10) Pulse width modulation outputs (PWM) 14-bit PWM: 3 channels (for controlling capstan, drum and tuner) 8-bit PWM: 9 channels (for controlling volume) Carrier frequency: 39.1 kHz (at 20 MHz) (11) 24-bit time base counter capture circuit (Capture 0) (18-bit timing data 6-bit trigger data) with 8-stages FIFO: 1 channel Capture input sources: Remote-control-input (RMTIN), V.sync, CTL, Drum-PG, general (1 channel) Accuracy: 400 ns (at 20 MHz) (12) 17-bit time base counter capture circuit (Capture 1/2) (16-bit timing data 1-bit trigger data): 2 channel Capture input sources: Drum-FG, Capstan-FG Accuracy: 100 ns (at 20 MHz) (13) VISS/VASS detection circuit (VISS/VASS) CTL duty detection VASS data 16-bit latch (14) Composite-sync-signal (C.sync) input (CSYNC) Vertical-sync-signal (V.sync) separation (15) Head Amp switch/Color Rotary control (HA/CR) (16) Pseudo-V/H generator (PV/PH) (17) 8-bit AD converter (ADC): 16 channels Conversion speed: 95states (9.5 s at 20 MHz) (18) Serial bus I/F 8-bit synchronous (SIO0, 1) : 2 channels UART I2C bus : 1 channel : 1 channel/2 ports Multi - Master function/Master transfer with micro DMA.
(19) Watch dog timer (WDT) (20) Interrupt controller (INTC) CPU: 8 sources SWI instruction, and illegal instruction 7-level priority can be set. Internal: 21 sources External: 5 sources
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(21) I/O ports 57 I/O ports (multiplexed functional pins) 8 input ports (P40/AIN3 to P47/AIN10: These pins are also used as analog input for AD converter.) 4 output ports (P24/A20 to P27/A23: These pins are also used as address bus outputs.) (22) Standby function: 4 halt modes (RUN, IDLE2, IDLE1, STOP) (23) System clock function Dual clock operation 20 MHz (High-speed: normal)/32 kHz (Low-speed: slow) 17-bit Real Time Counter built in (24) Operating Voltage Vcc Vcc (25) Package 120 pin QFP 28 mm 28 mm (Pin pitch: 0.8 mm) Type name: P-QFP120-2828-0.80B 2.7 to 5.5 V (at 32 kHz) 4.5 to 5.5 V (at 20 MHz)
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P75/SO0 P76/SI0 P77/SCK0 PB2/SO1/SI1 PB3/SCK1 P73/SDA0 P74/SCL0 PB4/SDA1 PB5/SCL1 P70/TXD P71/RXD P72/ CTS PWM0 PWM1 PA3/PWM2 PA4/ WR PA5/PWM3/ HWR P60/PWM4/ CS0 P61/PWM5/ CS1 P62/PWM6/ CS2 P63/PWM7 P64/PWM8 P65/PWM9 P66/PWM10 P67/PWM11 P57/TI0/AIN2 INT2 P52/INT2/TI1 P51/INT3/TI2 P50/INT4/TI3
Serial I/O (SIO0) Serial I/O (SIO1)
DVCC1, 2, 3 DGND1, 3
I CBUS I/F 2 (I C bus)
2
900/L CPU
XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC F
High Speed OSC (20 MHz) Low Speed OSC (32 kHz) CLK
X1 X2
PB0/XT1 PB1/XT2
EA
Serial I/O (UART)
Real Time Counter (RTC) CPU INT
RESET
14-Bit PWM (3ch) RAM (8 KB)
Interrupt Controller INT2, 3, 4 Others INT
P54/INT0 P53/INT1
CS/WAIT Controller (3ch) 8-Bit PWM (9ch)
8-Bit Timer (TC0)
to AD
Watchdog Timer (WDT) Time Base Timer (TBC)
AM8/16 D0 to D7 D8 to D15 A0 to A7 A8 to A15 A16 to A19
RD
16-Bit Timer (TC1) INT3 16-Bit Timer INT4 (TC2) 16-Bit Timer (TC3)
to AD
P24/A20 to P27/A23
Capture (Capture 0, 1, 2) VS
V-Separation
8-Bit AD Converter (16 ch)
ADREF P40 to 47/AIN3 to 10 PC0 to 4/AIN11 to 15 DGND2 (ADGND) P86/CSYNCIN
P56/TI4/AIN1 P55/TI5/AIN0
16-Bit Timer (TC4) 16-Bit Timer (TC5)
to AD
CSYNC RMT-Input Ext.-Input
RMTU, RMTD EXT CTL, CFG, DFG, DPG CFGTM
P82/RMTIN P83/EXT
P93/TPG03 P91/TPG01 P96/TPG10 P97/TPG11 P92/TPG02 P94/TPG04 P90/TPG12 P95/TPG13 PA1/HA(TPG05) PA2/CR(TPG00) P87/COMPIN
Timing Pulse Generator (TPG)
Capture Input (CAPIN) VISS/VASS CTL Duty Detector PCTL HS PV/PH
P84/DPGIN P85/CFGIN P81/DFGIN P80/CTLIN
Head Amp SW Colour Rotary (HA/CR)
TPG02, 04
PA0/PVPH
Figure 1.1 TMP93C071 block diagram
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2.
Pin Assignment And Functions
The assignment of input and output pins for the TMP93C071, their names and functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93C071.
PA4/WR PA3/PWM2 PWM1 PWM0 PA2/CR (TPG00) PA1/HA (TPG05) PA0/PVPH P27/A23 P26/A22 P25/A21 P24/A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 90 85 80 75 70 65 61
PA5/PWM3/ HWR P60/PWM4/ CS0 P61/PWM5/ CS1 P62/PWM6/ CS2 P63/PWM7 P64/PWM8 P65/PWM9 P66/PWM10 P67/PWM11 P70/TXD P71/RXD P72/ CTS
RD
91
60
95
55
100
50
AM8/ 16 DVCC3 P73/SDA0 P74/SCL0 P75/SO0 P76/SI0 P77/SCK0 DVCC1 X1 X2 DGND1
RESET
TMP93C071F QFP120
105 45
TOPVIEW
110
40
115
35
PB0/XT1 PB1/XT2
EA
PB2/SO1/SI1 PB3/SCK1
120 10 15 20 25 30 1 5
31
A0 DGND3 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P97/TPG11 P96/TPG10 P95/TPG13 P94/TPG04 P93/TPG03 P92/TPG02 P91/TPG01 P90/TPG12 P87/COMPIN P86/CSYNCIN P85/CFGIN P84/DPGIN
PB4/SDA1 PB5/SCL1 P50/INT4/TI3 P51/INT3/TI2 P52/INT2/TI1 P53/INT1 P54/INT0 P55/TI5/AIN0 P56/TI4/AIN1 P57/TI0/AIN2 DVCC2 ADREF DGND2 (ADGND) P40/AIN3 P41/AIN4 P42/AIN5 P43/AIN6 P44/AIN7 P45/AIN8 P46/AIN9 P47/AIN10 PC0/AIN11 PC1/AIN12 PC2/AIN13 PC3/AIN14 PC4/AIN15 P80/CTLIN P81/DFGIN P82/RMTIN P83/EXT
Figure 2.1.1 Pin assignment (120-pin QFP)
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2.2
Pin Names and Functions
The names of input/output pins and their functions are described below. Table 2.2.1 Pin names and function (1/4) Pin Name Number of Pins
16 20 4 1 1 1 1 2 1 1 1 8 5 1
I/O
I/O (3-state) Output Output Output Output Input Input Input I/O I/O Input I/O Output Input Input Input I/O Input I/O Input Input I/O Input Input I/O Input Input I/O Input I/O Input I/O Input Input I/O Input Input I/O Input Input Data: Bits 0 to 15 of data bus
Functions
D0 to D15 A0 to A19 A20 to A23 P24 to P27
RD
Address: Bits 0 to 19 of address bus Address: Bits 20 to 23 of address bus Port 2: Output port Read: strobe signal for reading external memory Data bus width select input (only 8 bits or 8 bits/16 bits) External access: Always set to "0" Reset: Initializes LSI.(with pull-up R) High Frequency Oscillator connecting pins (20 MHz) Port B0: I/O port (Open-drain output) Low Frequency Oscillator connecting pin (32 kHz) Port B1: I/O port (Open-drain output) Low Frequency Oscillator connecting pin (32 kHz) AD reference Voltage input Port 4: Input ports Analog input: Analog input signal for AD converter Port C: PC0 to PC4 I/O port that allows selection of I/O on a bit basis. Analog input: Analog input signal for AD converter Port 50: I/O port (Schmitt input) External Interrupt request input 4 Rising edge/Falling edge programable 16-bit timer3 (TC3) Input 3 Port 51: I/O port (Schmitt input) External Interrupt request input 3 Rising edge/Falling edge programable 16-bit timer2 (TC2) Input 2 Port 52: I/O port (Schmitt input) External Interrupt request input 2 Rising edge/Falling edge programable 16-bit timer1(TC1) Input 1 Port 53: I/O port (Schmitt input) External Interrupt request input 1: Rising edge/ Level programable Port 54: I/O port (Schmitt input) External Interrupt request input 0: Rising edge/ Level programable Port 55: I/O port (Schmitt input) 16-bit timer5 (TC5) Input 5 Analog input: Analog input signal for AD converter Port 56: I/O port (Schmitt input) 16-bit timer4 (TC4) Input 4 Analog input: Analog input signal for AD converter Port 57: I/O port (Schmitt input) 8-bit timer0 (TC0) Input 0 Analog input: Analog input signal for AD converter
AM8/ 16
EA
RESET
X1/X2 PB0 XT1 PB1 XT2 ADREF P40 to P47 AIN3 to AIN10 PC0 to PC4 AIN11 to AIN15 P50 INT4 TI3 P51 INT3 TI2 P52 INT2 TI1 P53 INT1 P54 INT0 P55 TI5 AIN0 P56 TI4 AIN1 P57 TI0 AIN2
1
1
1
1
1
1
1
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Table 2.2.1 Pin names and function (2/4) Pin Name
PWM0 PWM1 P60 PWM4
CS0
Number of Pins
1 1 1
I/O
Output Output I/O Output Output I/O Output Output I/O Output Output I/O Output I/O Output I/O Output I/O Output I/O Output I/O Output I/O Input I/O Input I/O I/O I/O I/O I/O Output I/O Input I/O I/O I/O Input I/O Input I/O Input
Functions
PWM (14-bit) output 0: PWM0 output Push-pull or open-drain output selectable PWM (14-bit) output 1: PWM1 output Push-pull or open-drain output selectable Port 60: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 4: PWM4 output Chip select 0: Output 0 when address is within specified address area. Port 61: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 5: PWM5 output Chip select 1: Output 0 when address is within specified address area. Port 62: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 6: PWM6 output Chip select 2: Output 0 when address is within specified address area. Port 63: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 7: PWM7 output Port 64: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 8: PWM8 output Port 65: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 9: PWM9 output Port 66: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 10: PWM10 output Port 67: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 11: PWM11 output Port 70: I/O port (Schmitt input), Push-pull or open-drain output selectable UART send data Port 71: I/O port (Schmitt input) UART receive data Port 72: I/O port (Schmitt input) UART clear to send Port 73: I/O port (Schmitt input), Push-pull or open-drain output selectable I2C bus SDA line 0 Port 74: I/O port (Schmitt input), Push-pull or open-drain output selectable I2C bus SCL line 0 Port 75: I/O port (Schmitt input), Push-pull or open-drain output selectable SIO0 send data 0 Port 76: I/O port (Schmitt input) SIO0 receive data 0 Port 77: I/O port (Schmitt input), Push-pull or open-drain output selectable SIO0 transfer clock input/output 0 Port 80: I/O port (Schmitt input) Capture input for Control signal (CTL) Port 81: I/O port (Schmitt input) Capture input for Drum-FG signal (DFG) Port 82: I/O port (Schmitt input) Capture input for Remote Control Input signal
P61 PWM5
CS1
1
P62 PWM6
CS2
1
P63 PWM7 P64 PWM8 P65 PWM9 P66 PWM10 P67 PWM11 P70 TXD P71 RXD P72
CTS
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
P73 SDA0 P74 SCL0 P75 SO0 P76 SI0 P77 SCK0 P80 CTLIN P81 DFGIN P82 RMTIN
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Table 2.2.1 Pin names and function (3/4) Pin Name
P83 EXT P84 DPGIN P85 CFGIN P86 CSYNCIN P87 COMPIN P90 TPG12 P91 TPG01 P92 TPG02 P93 TPG03 P94 TPG04 P95 TPG13 P96 TPG10 P97 TPG11 PA0 PVPH PA1 HA (TPG05) PA2 CR (TPG00) PA3 PWM2 PA4
WR
Number of Pins
1 1 1 1 1 1 1 1 1 1 1 1 1 1
I/O
I/O Input I/O Input I/O Input I/O Input I/O Input I/O Output I/O Output I/O Output I/O Output I/O Output I/O Output I/O Output I/O Output I/O Output 3-state I/O Output I/O Output I/O Output I/O Output I/O Output Output I/O I/O I/O I/O
Functions
Port 83: I/O port (Schmitt input) External Capture input (Rising edge only) Port 84: I/O port (Schmitt input) Capture input for Drum-PG signal (DPG) Port 85: I/O port (Schmitt input) Capture input for Capstan-FG signal (CFG) Port 86: I/O port (Schmitt input) Capture input for C.sync Port 87: I/O port (Schmitt input) Envelope Comparator Input (to HA/CR) Port 90: I/O port, Push-pull or open-drain output selectable TPG12: TPG output 12 Port 91: I/O port, Push-pull or open-drain output selectable TPG01: TPG output 01 Port 92: I/O port, Push-pull or open-drain output selectable TPG02: TPG output 02 (Internally connected to PV/PH Logic) Port 93: I/O port, Push-pull or open-drain output selectable TPG03: TPG output 03 Port 93: I/O port, Push-pull or open-drain output selectable TPG04: TPG output 04 (Internally connected to PV/PH Logic) Port 95: I/O port, Push-pull or open-drain output selectable TPG13: TPG output 13 Port 96: I/O port, Push-pull or open-drain output selectable TPG10: TPG output 10 Port 97: I/O port, Push-pull or open-drain output selectable TPG11: TPG output 11 Port PA0: I/O port Pseudo-V.sync, Pseudo-H.sync output (controlled by TPG02/04.) Port PA1: I/O port HA: Head amp switch output or TPG05 output Port PA2: I/O port schmitt CR: Colour Rotary output or TPG00 output Port A3: I/O port, PWM (14-bit ) output 2: PWM2 output Push-pull or open-drain output selectable Port A4: I/O port, Push-pull or open-drain output selectable Write: Strobe signal for writing data on pins D0 to D7 Port A5: I/O port, Push-pull or open-drain output selectable 8-bit PWM output 3: PWM3 output High write: Strobe signal for writing data on pins D8 to D15 Port PB2: I/O port (Schmitt input), Push-pull or open-drain output selectable SIO1 send data 1 and receive data 1 (Internally connected) Port PB3: I/O port (Schmitt input), Push-pull or open-drain output selectable SIO1 transfer clock input/output 1
1 1 1 1 1
PA5 PWM3
HWR
PB2 SO1/SI1 PB3 SCK1
1 1
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Table 2.2.1 Pin names and function (4/4) Pin Name
PB4 SDA1 PB5 SCL1 DVCC1, 2, 3 DGND1, DGND2 (ADGND), DGND3
Number of Pins
1 1 3 3 I/O I/O I/O I/O
I/O
Functions
Port PB4: I/O port (Schmitt input), Push-pull or open-drain output selectable I2C bus SDA line 1 Port PB5: I/O port (Schmitt input), Push-pull or open-drain output selectable I2C bus SCL line 1 Power supply pins All of these pins should be connected to power source. GND pins (0 V) All of these pins should be connected to GND (0 V) line. DGND2 are also used as ADGND for AD converter.
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3.
Operation
This section describes the functions and basic operational blocks of TMP93C071 devices. See the "7. Points of Concern and Restrictions" for the using notice and restrictions for each block.
3.1
CPU
TMP93C071 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous section). This section describes CPU functions unique to the TMP93C071 that are not described in the previous section.
3.1.1
Reset
To reset the TMP93C071, the RESET input must be kept at 0 for at least 10 system clocks. (1 s at 20 MHz) within the operating voltage range and with a stable oscillation. When reset is accepted, the CPU sets as follows: Program Counter (PC) according to Reset Vector that is stored FFFF00H to FFFF02H. PC (7 to 0) PC (15 to 8) PC (23 to 16) stored data in location FFFF00H stored data in location FFFF01H stored data in location FFFF02H
Stack pointer (XSP) for system mode to 100H. IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.) MAX bit of status register to 1. (Sets to maximum mode) Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.) When reset is released, instruction execution starts from PC (reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows: Initializes built-in I/O registers as per specifications. Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode.
Note:
By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed.
Figure 3.1.1 show the reset timing chart of TMP93C071.
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Total 2 cycles omitted
X1
Internal CLK Sampling Sampling
RESET
A0 to 23 (P60 to 62 input mode)
FFFF00H
CS0 to 2
D0 to 15
Data input Read
RD
Figure 3.1.1 TMP93C071 reset timing chart
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Data output (PA4 input mode) (PA5 input mode) (input mode) Note: High-Impedance
(0 WAIT Read cycle after reset.)
D0 to 15
WR
Write
HWR
P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA5 PB0 to PB5 PC0 to PC4
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a. With fixed 16-bit data bus, external 16-bit data bus or 8-bit data bus is selectable Set this pin to L. The external data bus width is set by the chip select/wait control register which is described in section 3.6.3. It is necessary to set the program memory to be accessed to 16-bit data bus after reset. With fixed external 8-bit data bus Set this pin to H. The values of bit 4 , and in the chip select/wait control register described in section 3.6.3 are invalid. The external 8-bit data bus is fixed.
b.
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3.2
Memory Map
Figure 3.2.1 is a memory map of the TMP93C071.
000000H Internal I/O (144 Bytes) 000090H Direct Area (n)
Internal RAM (8 Kbytes)
000100H
002090H
64-Kbyte Area (nn)
External Area
16-Mbyte Area (r32) ( r32) (r32 ) (r32 d8/16) (r32 r8/16) (nnn) FFFF00H Interrupt Vector Table Area (256 Bytes) FFFFFFH
Internal Area
Figure 3.2.1 Memory map
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4.
4.1
Electrical Characteristics(Preliminary)
Absolute Maximum Rating
Parameter
Power Supply Voltage Input Voltage (Including Open-drain ports) Output Current (Per 1 pin) Output Current (Per 1 pin) Output Current (total) Output Current (total) Power Dissipation (Ta Storage Temperature Operating Temperature 70C) Soldering Temperature (10sec) Vcc VIN VOUT IOL IOH IOL IOH PD TSOLDER TSTG TOPR
Symbol
Rating
0.5 to 6.5 0.5 to Vcc 0.5 to Vcc 3.2 3.2 120 120 600 260 65 to 150 20 to 70 0.5 0.5
Unit
V V V mA mA mA mA mW C C C
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
4.2
DC Characteristics (1/2)
Ta 20 to 70C
Parameter
Power Supply Voltage D0 to D15 P4, P6, P9, PA, PB0, 1, PC Input Low Voltage
RESET ,
Symbol
Vcc VIL (TTL) VIL1 (CMOS) VIL2 (Schmitt) VIL3 (Fixed) VIL4 (Xtal) VIH (TTL) VIH1 (CMOS) VIH2 (Schmitt) VIH3 (Fixed) VIH4 (Xtal) Vcc Vcc Vcc Vcc fc fs Vcc Vcc
Condition
4 to 20 MHz 30 to 34 kHz 4 .5 V 4.5 V
Min
4.5 2.7
Typ.
Max
5.5 0.8 0.6 0.3 Vcc
Unit
V
INT0 to 4, P5, P7, P8, PB2 to 5
EA , AM8/ 16
0.3 2.7 to 5.5 V
0.25 Vcc
V
0.3 0.2 Vcc 4.5 V 4.5 V 2.2 2.0 0.7 Vcc
X1 D0 to D15 P4, P6, P9, PA, PB0, 1, PC Input High Voltage
RESET ,
INT0 to 4, P5, P7, P8, PB2 to 5
EA , AM8/ 16
0.75 Vcc 2.7 to 5.5 V Vcc 0.3
Vcc
0.3
V
X1
0.8 Vcc
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DC Characteristics (2/2)
Ta 20 to 70C
Parameter
Output Low Voltage Output High Voltage
Symbol
VOL VOH VOH1
Condition
IOL 1.6 mA (Vcc 2.7 to 5.5 V) IOH (Vcc IOH (Vcc 0.0 0.2 400 A 2.7 to 5.5 V) 700 A 4.5 to 5.5V) Vin Vin Vcc Vcc 0.2
Min
Typ.
Max
0.45
Unit
V
2.4 V 4.1 0.02 0.05 2.0 50 80 5 A 10 6.0 150 200 10 pF V
Input Leakage Current Output Leakage Current Power Down Voltage
RESET
ILI ILO VSTOP RRST CIO
VIL2 0.2 Vcc, VIH2 0.8 Vcc Vcc Vcc 5V 3V 10% 10%
Pull Up Resistor Pin Capacitance Schmitt Width RESET , INT0 to 4, P5, P7, P8, PB2 to 5 NORMAL RUN IDLE2 IDLE1 SLOW RUN IDLE2 IDLE1 STOP
osc 1 MHz/100 mVpp 1.0 28 Vcc 5 V 10% fc 20 MHz 22 16 3.5 40 32 27 17 Vcc 2.7 to 5.5 V 0.2
VTH
V 45 35 25 8 70 45 40 30 10 A A mA
ICC
Vcc 3 V 10% fs 32.768 kHz (Typ: Vcc 3.0 V)
Note 1: Typical value are for Ta
25C and Vcc
5 V unless otherwise noted.
Note 2: Icc measurement conditions (NORMAL, SLOW). Only CPU is operational; output pins are open and input pins are fixed. Note 3: P55, P56 and P57 have a hysteresis when TI5, TI4 and TI0 is enabled.
4.3
AD Conversion Characteristics
Ta 20 to 70C, Vcc 4.5 to 5.5 V
Parameter
Analog Reference Voltage Supply Analog Input Voltage Range Analog Current for ADREF Total tolerance (excludes quantization error) (Ta 25C, Vcc ADREF 5V)
Symbol
ADREF ADGND VAIN IREF ET
Min
Vcc 1.5 Vss ADGND
Typ.
Vcc Vss 1.0
Max
Vcc Vss ADREF 1.5 3
Unit
V V V mA LSB
93C071-219
2003-03-31
TMP93C071
4.4
AC Electrical Characteristics(Preliminary) (Separated Bus)
(1) Vcc = 5 V 10% Parameter
OSC.Period ( X) A0 to 23 Valid A0 to 23 Valid
RD fall RD Low width RD rise RD / WR / HWR Fall RD / WR / HWR Rise
Ta
20 to 70C
Symbol
tOSC tAC tCA tAD tRD tRR tHR tWW tDW tWD tAPH tAPH2 tCP
Variable Min
50 1.0X 0.5X 25 25 3.5X 2.5X 2.5X 0 2.5X 2.0X 0.5X 2.5X 40 55 15 2.5X 50 200 120 175 40 65 60 85 0 85 45 10
20 MHz Max
250
Min
50 25 0
Max
Unit
ns ns ns
A0 to 23 Hold
D0 to 15 input
110 65
ns ns ns ns ns ns ns
D0 to 15 input D0 to 15 Hold
WR / HWR Rise
WR / HWR Low Pulse Width
D0 to 15 Valid
WR / HWR Rise
D0 to 15 Hold Port Input Port Hold Port Valid
A0 to 23 Valid A0 to 23 Valid
WR / HWR Rise
5 200
ns ns ns
AC Test Condition: Output Level: High 2.2 V, Low 0.8 V, CL 50pF (D0 to D15, A0 to 23, RD , WR , HWR , CS0 to CS2 : CL Input Level: High High 2.4 V/Low 0.45 V (D0 to D15) 0.8 Vcc/Low 0.2 Vcc (except D0 to D15)
Ta 20 to 70C
100pF)
(2) Vcc
3V 10% Parameter Symbol
tOSC
RD / WR / HWR Fall
Variable Min
29400 1.0X 0.5X 50 40 3.5X 2.5X 2.5X 0 2.5X 2.0X 0.5X 2.5X 40 120 40 2.5X 50 200 120 40 125 115
Max
33300
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns
OSC.Period(= X) A0 to 23 Valid A0 to 23 Valid
RD fall RD Low width RD rise RD / WR / HWR Rise
tAC tCA tAD tRD tRR tHR tWW tDW tWD tAPH tAPH2 tCP
A0 to 23 Hold
D0 to 15 input
D0 to 15 input D0 to 15 Hold
WR / HWR Rise
WR / HWR Low Pulse Width
D0 to 15 Valid
WR / HWR Rise
D0 to 15 Hold Port Input Port Hold Port Valid
A0 to 23 Valid A0 to 23 Valid
WR / HWR Rise
AC Test Condition: Output Level: High Input Level: High 0.7 0.9 Vcc, Low Vcc, Low 0.3 0.1 Vcc, CL Vcc 50pF
93C071-220
2003-03-31
TMP93C071
(1) Read cycle timing chart
tOSC
X1/XT1
A0 to 23
CS
tAD
RD
tCA tRR tHR tRD
tAC
D0 to 15 tAPH2 tAPH Port Input Port Input
D0 to D15 Input
(2) Write cycle timing chart
WR
,
HWR
tWW tWD tDW
D0 to 15
D0 to D15 Output tCP
Port Output
93C071-221
2003-03-31
TMP93C071
4.5
Serial Channel Timing Chart
(1) I2C bus
Start Command tGSTA1 SDA tODAT1 Stop Command tGSTP1 tODAT3
tFSDA SCL
tRSDA
tRSCL
tFSCL
tGSTA2
tSUODAT
tHDODAT
tHIGH
tLOW
tGSTP2
tCYCSCL
Parameter
SCL cycle SCL low pulse width SCL High pulse width SDA Rising Time SDA Falling Time SCL Rising Time SCL Falling Time (Note 1) (Note 1) (Note 1) (Note 1)
Symbol
tCYCSCL tLOW tHIGH tRSDA tFSDA tRSCL tFSCL tGSTA1 tGSTA2 TODAT1 tSUODAT
Min
16N/f 8N/f 12/f
Typ.
8N/f
Max
Unit
s s s s s s s
10/f
The time from start command write to start sheecense Start condition hold time, start generation of the first clock after this Delay time from SCL rising to data output Set up time of data output SCL rising (Note 2) (Note 2)
6/f 8N/f 8N/f (10/f tFSCL) 3/f 6/f 8N/f 8N/f 14/f 14/f 4/f 10/f
s s s s
The time of holding data for SCL rising
(Note 3)
tHODAT tGSTP1 tGSTP2 tGSTP3
s s s s
The time from stop command write to starting stop sheecense The time from SDA falling to SCL rising (during stop sheecense) Stop condition set up time
Note 1: The time of rising/falling depend on the feature of bus interface. Note 2: The worst case is at the first bit of slave address. Note 3: The worst case is at the acknowledge bit.
Frequency divisor set in N: I2CCR3 Internal system clock (fsys) f/2 (f fc or fs)
93C071-222
2003-03-31
TMP93C071
(2) SIO0, 1
tSCH SCLK tSCL tSCY
SO tSDO SI tSSDI tSHDI
SIO AC Electrical Characteristics (SCLK external input) Parameter
SCLK cycle SCLK High pulse width SCLK Low pulse width SCLK shift edge SCLK shift edge SCLK shift edge SO delay SI setup SI hold
Ta
20 to 70C Vcc
5V
10%
Symbol
tSCY tSCH tSCL tSDO tSSDI tSHDI
Variable Min
25X (24X) tSCY/2 50 (tSYC/2) tSCY/2 50 (tSYC/2) 6X X 6X 50 50 50 0 350
20 MHz Max Min
1.6 (0.8) 750 (400) 750 (400) 350
Max
Unit
us ns ns ns ns ns
Note: These are value when SCxMOD don't be disabled under transferring. (SCLK internal output) Parameter
SCLK cycle SCLK High pulse width SCLK Low pulse width SCLK shift edge SCLK shift edge SCLK shift edge SO delay SI setup SI hold
Ta
20 to 70C Vcc
5V
10%
Symbol
tSCY tSCH tSCL tSDO tSSDI tSHDI
Variable Min
24X tSCY/2 tSCY/2 X 0 50 50 50
20 MHz Max
27X
Min
0.8 350 350 100 0
Max
6.4 3200 3200 100
Unit
us ns ns ns ns ns
tSCY/2 tSCY/2 X 50
93C071-223
2003-03-31

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